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siliconwitchsiliconwitch
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Merge pull request #254 from brilliantlabsAR/jpeg-merging
JPEG optimisations
2 parents 1271c82 + 9376cb4 commit a97dfb1

18 files changed

+23805
-25321
lines changed

‎source/fpga/fpga_application.h

+23,406-24,944
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‎source/fpga/modules/camera/jpeg_encoder/jenc/bit_pack.sv

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/*
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* Authored by: Robert Metchev / Chips & Scripts (rmetchev@ieee.org)
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*
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* CERN Open Hardware Licence Version 2 - Permissive
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*
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* Copyright (C) 2024 Robert Metchev
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*/
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module bit_pack (
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//packed code+coeff
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input logic [63:0] in_data,
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input logic [6:0] in_nbits,
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input logic in_tlast,
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input logic in_valid,
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output logic in_hold,
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output logic [31:0] out_data,
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output logic [2:0] out_nbytes,
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output logic out_tlast,
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output logic out_valid,
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input logic out_hold,
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input logic clk,
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input logic resetn
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);
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// 1.) 64-bit to 32-bit align: There will be extremely rarely more than 32 bits.
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// Stall during 1st 32 bits.
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logic [31:0] in32_data;
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logic [5:0] in32_nbits;
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logic in32_tlast;
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logic in32_valid;
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logic in32_hold;
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logic long_in;
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always @(posedge clk)
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if (!resetn) begin
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in32_valid <= 0;
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long_in <= 0;
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end
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else if (~(in32_hold & in32_valid)) begin
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in32_valid <= in_valid;
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if (long_in)
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long_in <= 0;
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else if (in_valid & in_nbits > 32)
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long_in <= 1;
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end
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always @(posedge clk)
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if (~(in32_hold & in32_valid))
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if (long_in) begin
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in32_nbits <= in_nbits - 32;
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in32_data <= in_data;
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in32_tlast <= in_tlast;
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end
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else if (in_valid)
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if (in_nbits > 32) begin
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in32_nbits <= 32;
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in32_data <= in_data >> 32;
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in32_tlast <= 0;
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end
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else begin
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in32_nbits <= in_nbits;
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in32_data <= in_data >> 32;
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in32_tlast <= in_tlast;
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end
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// Stall to split 32+ into 32 + remainder
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always_comb in_hold = (in32_hold & in32_valid) | (~long_in & in_nbits > 32); // goes out
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// 2.) incoming: 32 bits max = 4 bytes
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// send data when more than 31 bits in storage
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logic [5:0] bit_count, next_bit_count, next_bit_count_incr, next_bit_count_decr;
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logic [63:0] bit_packer, next_bit_packer, next_bit_packer_load;
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logic [5:0] next_bit_packer_shift;
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logic tlast_cycle, next_tlast_cycle;
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logic next_out_tlast;
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always_comb out_data = (bit_packer >> 32) | (out_tlast ? (32'hffffffff >> bit_count) : 0);
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always_comb next_bit_count = bit_count + next_bit_count_incr - next_bit_count_decr;
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always_comb next_bit_packer = (bit_packer << next_bit_packer_shift) | (next_bit_packer_load << (32 + next_bit_count_decr - bit_count));
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always_comb begin
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if (out_tlast) begin
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next_bit_count_decr = bit_count;
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next_bit_packer_shift = 32;
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end
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else if (bit_count >= 32) begin
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next_bit_count_decr = 32;
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next_bit_packer_shift = 32;
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end
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else begin
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next_bit_count_decr = 0;
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next_bit_packer_shift = 0;
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end
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if (in32_valid & ~in32_hold) begin
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next_bit_count_incr = in32_nbits;
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next_bit_packer_load = in32_data;
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end
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else begin
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next_bit_count_incr = 0;
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next_bit_packer_load = 0;
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end
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if (tlast_cycle)
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next_tlast_cycle = ~out_tlast;
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else if (in32_valid)
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next_tlast_cycle = in32_tlast;
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else
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next_tlast_cycle = tlast_cycle;
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end
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always @(posedge clk)
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if (!resetn) begin
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bit_count <= 0;
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tlast_cycle <= 0;
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out_tlast <= 0;
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out_valid <= 0;
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bit_packer <= 0;
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end
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else if (~(out_hold & out_valid)) begin
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bit_count <= next_bit_count;
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tlast_cycle <= next_tlast_cycle;
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out_tlast <= next_tlast_cycle & next_bit_count <= 32;
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out_valid <= (next_tlast_cycle & next_bit_count <= 32) | next_bit_count >= 32; //always_comb out_valid = out_tlast | bit_count >= 32;
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bit_packer <= next_bit_packer;
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end
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always @(posedge clk)
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if (~(out_hold & out_valid))
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out_nbytes <= (next_tlast_cycle & next_bit_count <= 32) ? (next_bit_count + 7) >> 3 : 4; // always_comb out_nbytes = out_tlast ? (bit_count + 7) >> 3 : 4;
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always_comb in32_hold = (out_hold & out_valid) | (tlast_cycle & ~out_tlast);
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endmodule

‎source/fpga/modules/camera/jpeg_encoder/jenc/bitpacker.sv

-80
This file was deleted.

‎source/fpga/modules/camera/jpeg_encoder/jenc/byte_pack.sv

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/*
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* Authored by: Robert Metchev / Chips & Scripts (rmetchev@ieee.org)
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*
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* CERN Open Hardware Licence Version 2 - Permissive
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*
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* Copyright (C) 2024 Robert Metchev
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*/
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module byte_pack (
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//packed code+coeff
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input logic [5:0] codecoeff_length,
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input logic [51:0] codecoeff,
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input logic codecoeff_tlast,
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input logic codecoeff_valid,
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output logic codecoeff_hold,
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output logic [31:0] out_data,
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output logic out_tlast,
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output logic out_valid,
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input logic out_hold,
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input logic clk,
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input logic resetn
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);
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// Pack up to 52 bits into 4 byte words
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logic [31:0] data_0;
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logic [2:0] nbytes_0;
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logic tlast_0;
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logic valid_0;
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logic hold_0;
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bit_pack bit_pack_0 (
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.in_data ({codecoeff, 12'h0}),
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.in_nbits ({1'b0, codecoeff_length}),
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.in_tlast (codecoeff_tlast),
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.in_valid (codecoeff_valid),
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.in_hold (codecoeff_hold),
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.out_data (data_0),
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.out_nbytes (nbytes_0),
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.out_tlast (tlast_0),
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.out_valid (valid_0),
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.out_hold (hold_0 & valid_0),
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.*
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);
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// pad 0xFF with 0x00
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logic [63:0] data_1;
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logic [3:0] nbytes_1;
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logic tlast_1;
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logic valid_1;
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logic hold_1;
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ff00 ff00 (
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.in_data (data_0),
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.in_nbytes (nbytes_0),
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.in_tlast (tlast_0),
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.in_valid (valid_0),
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.in_hold (hold_0),
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.out_data (data_1),
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.out_nbytes (nbytes_1),
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.out_tlast (tlast_1),
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.out_valid (valid_1),
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.out_hold (hold_1 & valid_1),
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.*
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);
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// Pack up to 8 bytes into 4 byte words
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bit_pack bit_pack_1 (
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.in_data (data_1),
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.in_nbits ({nbytes_1, 3'h0}), // bytes -> bits
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.in_tlast (tlast_1),
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.in_valid (valid_1),
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.in_hold (hold_1),
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.out_nbytes ( ), // always full 32 bits/4 bytes
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.out_hold (out_hold & out_valid),
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.*
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);
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endmodule

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